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US 12,014,771 B2Granted
Method of pseudo-triple-port SRAM datapaths
AssigneeQUALCOMM Incorporated
InventorsChangho Jung, Arun Babu Pallerla, Chulmin Jung
Life of this patent
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Abstract
A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.
Claims7
A method for a memory, comprising:
- in a read cycle responsive to a beginning of a cycle memory clock signal, performing a first single-ended read through a first bit line to a first bitcell in a column to charge the first bit line to a power supply voltage;
- while performing the first single-ended read, performing a second single-ended read through a second bit line to a second bitcell in the column to discharge the second bit line;
- and
- in a write cycle following the read cycle, writing to the first bitcell through the first bit line and through the second bit line, wherein the first bit line remains charged to the power supply voltage from an end of the read cycle to an end of the write cycle and the second bit line remains discharged from the end of the read cycle to the end of the write cycle.
1 more element
Dependencies are inferred from the claim text.