DRAM computation circuit and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChieh Lee, Chia-En Huang, Yi-Ching Liu, Wen-Chang Cheng, Yih Wang
Life of this patent
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Abstract
A memory circuit includes first and second circuits. The first circuit includes a DRAM array including a plurality of bit lines, and the second circuit includes a computation circuit including a sense amplifier circuit. A boundary layer is positioned between the first and second circuits, and the boundary layer includes a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit.
Claims20
A memory circuit comprising:
- a first circuit comprising a dynamic random-access memory (DRAM) array, wherein the DRAM array comprises a plurality of bit lines;
- a second circuit comprising a computation circuit, wherein the computation circuit comprises a sense amplifier circuit;
- and
- a boundary layer positioned between the first and second circuits,
- wherein
- the boundary layer comprises a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit, and
- the plurality of bit lines electrically connected to the sense amplifier circuit by the plurality of via structures are an entirety of the bit lines electrically connected to the sense amplifier circuit.
A neural network circuit comprising:
- a first circuit;
- a second circuit;
- a boundary layer positioned between the first and second circuits;
- and
- a memory circuit comprising:
- an array of dynamic random-access memory (DRAM) cells positioned in the first circuit;
- a computation circuit positioned in the second circuit, wherein the computation circuit comprises a sense amplifier circuit;
- and
- a plurality of bit lines coupled to each of the array of DRAM cells and the computation circuit,
- wherein
- each bit line of the plurality of bit lines comprises a via structure positioned in the boundary layer, and
- the plurality of bit lines comprising the via structures positioned in the boundary layer are an entirety of the bit lines electrically connected to the sense amplifier circuit.
A method of manufacturing an integrated circuit (IC) device, the method comprising:
- building or packaging a dynamic random-access memory (DRAM) array in a first IC device layer;
- building or packaging a computation circuit in a second IC device layer;
- and
- forming via structures electrically connecting bit lines of the DRAM array to a sense amplifier circuit of the computation circuit,
- wherein the forming the via structures electrically connecting the bit lines of the DRAM array to the sense amplifier circuit comprises electrically connecting an entirety of the bit lines electrically connected to the sense amplifier circuit.
Dependencies are inferred from the claim text.