Double data rate (DDR) memory controller apparatus and method

A double data rate memory controller for self-calibration, the controller comprising:

• a data capture register configured to be implemented in a byte lane of a physical clocking domain (phy-domain), configured to be clocked by a delayed version of a strobe signal, and further configured to generate, in response to receiving read data that has not passed through a delay element, a first output in the phy-domain;
• a first core domain register coupled the data capture register to receive the first output in a core clock domain;
• a phy-domain delay element configured to generate the delayed version of the strobe signal to clock the data capture register;
• a first core clock delay element coupled to the first core domain register, the first core clock delay element configured to generate a capture clock signal, represents a delayed version of a core clock signal, to clock the first core domain register;
• and
• a second core domain register coupled to the first core domain register and configured to generate, in response to being clocked by the core clock signal, a second output.