Memory device including row hammer preventing circuitry and an operating method of the memory device

A memory device, comprising:

• a memory cell array including a plurality of memory cells;
• and
• a memory controller including a table, which includes a count value representing a hit count and address bits of a plurality of entries, a safe bit representing whether each of a plurality of target rows is accessed twice or more during a refresh interval, and a safe bit counter representing the number of the safe bits having a logic low;
• and
• a row hammer preventing circuitry configured to identify masking entries, on which a masking comparison is to be performed, among a plurality of entries stored in the table on the basis of a value of the safe bit counter and to determine a hit or a miss on the basis of whether other bits except a most significant bit among address bits of an access-requested target row match other bits except a most significant bit among address bits of the masking entries.

An operating method of a memory device, the operating method comprising:

• receiving an access command corresponding to a target row;
• identifying a masking entry among a plurality of entries corresponding to access-requested rows;
• performing a first comparison in which it is determined whether other bits except a most significant bit in address bits of the masking entry matches other bits except a most significant bit in address bits of the target row;
• when a hit occurs as a result of the first comparison, increasing a hit count of a masking entry corresponding to the hit;
• and
• when the hit count is greater than a first threshold value, generating a control signal indicating an additional refresh is to be performed on rows respectively adjacent to two rows corresponding to the masking entry.