Memory cell, semiconductor device having the same, and methods of manufacturing the same

A semiconductor device, comprising:

• a first interconnect structure, disposed on a substrate;
• a memory cell, disposed on the first interconnect structure, wherein the memory cell comprises:
• a bottom electrode, electrically coupled to the first interconnect structure;
• a memory layer, disposed over the bottom electrode;
• a first thermal insulating layer, interposed between the memory layer and the bottom electrode, wherein a thermal conductivity of the first thermal insulating layer is less than a thermal conductivity of the memory layer;
• a top electrode, disposed over the memory layer, wherein the memory layer is disposed between the top electrode and the first thermal insulating layer;
• and
• a protection layer, extending along the top electrode, the first thermal insulating layer, the memory layer and the bottom electrode;
• and
• a second interconnect structure, disposed on the memory cell and electrically coupled to the top electrode, wherein the protection layer further extends onto a side of the second interconnect structure, wherein in a cross-section of the semiconductor device along a stacking direction of the first interconnect structure and the second interconnect structure, the protection layer covers a sidewall of the bottom electrode and is between the first interconnect structure and the second interconnect structure.

A method of manufacturing a memory cell, comprising:

• forming a bottom electrode;
• forming a first buffer material, a storage element material and a top electrode material over the bottom electrode;
• patterning the top electrode material, the storage element material and the first buffer material to form a top electrode, a storage element layer and a first buffer layer, wherein the storage element layer is disposed between the bottom electrode and the top electrode, the first buffer layer is interposed between the bottom electrode and the storage element layer, and a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer, wherein the first buffer layer is in contact with a first surface of the bottom electrode;
• and
• disposing a protection layer covering the top electrode, the storage element layer and the first buffer layer, the bottom electrode being free of the protection layer, wherein a bottommost surface of the protection layer is substantially level with or above the first surface of the bottom electrode in a stacking direction of the bottom electrode and the first buffer layer.