Multi-level hydrogen barrier layers for memory applications and methods of fabrication

A method of fabricating a device structure, the method comprising:

• forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region;
• depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect;
• forming an electrode structure on the first conductive interconnect by a first process comprising:
• etching a first opening in the etch stop layer;
• depositing a first conductive hydrogen barrier layer in the first opening;
• and
• depositing a first conductive material on the first conductive hydrogen barrier layer;
• forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack;
• depositing a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer;
• forming a via electrode on the memory device by a second process comprising:
• forming a second opening in the second dielectric;
• depositing a second conductive hydrogen barrier layer on at least a portion of an uppermost surface of the memory device in the second opening;
• and
• depositing a conductive material on the second conductive hydrogen barrier layer;
• etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material;
• performing a planarization of the third dielectric, wherein the planarization forms a first portion of the third dielectric above the second dielectric and forms a second portion of the third dielectric directly laterally adjacent to the second dielectric;
• etching the third dielectric to form a trench opening above the via electrode;
• forming a contact electrode in the trench opening by depositing a third conductive hydrogen barrier layer on the via electrode in the trench opening and on the third dielectric, by depositing a second conductive material on the third conductive hydrogen barrier layer, and by planarizing to remove the second conductive material and the third conductive hydrogen barrier layer from above the third dielectric;
• etching the third dielectric to form a hanging trench;
• masking a portion of the hanging trench to form a via opening in the third dielectric below the hanging trench;
• and
• forming a via structure by depositing one or more conductive materials in the via opening and in the hanging trench.

A method of fabricating a device structure, the method comprising:

• forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region;
• depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect;
• forming an electrode structure on the first conductive interconnect by a first process comprising:
• etching a first opening in the etch stop layer;
• depositing a first conductive hydrogen barrier layer in the first opening;
• and
• depositing a first conductive material on the first conductive hydrogen barrier layer;
• forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack;
• depositing a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer;
• forming a via electrode on the memory device by a second process comprising:
• forming a second opening in the second dielectric;
• depositing a second conductive hydrogen barrier layer on at least a portion of an uppermost surface of the memory device in the second opening;
• and
• and depositing a second conductive material on the second conductive hydrogen barrier layer;
• etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material;
• depositing a fourth dielectric on the second dielectric, on the via electrode and on the third dielectric;
• etching the fourth dielectric to form a hanging trench above the second conductive interconnect, and a trench opening above the via electrode;
• masking the trench opening and a portion of the hanging trench and to form a via opening in the third dielectric below the hanging trench;
• depositing a liner layer in the via opening, in the hanging trench and in the trench opening and on an uppermost surface of the fourth dielectric;
• depositing a third conductive material simultaneously in the via opening, in the hanging trench and in the trench opening on the liner layer;
• and
• planarizing to remove the third conductive material and the liner layer from above the fourth dielectric and forming a contact electrode in the trench opening, a via structure in the via opening and a metal line in the hanging trench.