US 12,010,853 B2Granted

Methods for novel three-dimensional nonvolatile memory

AssigneeBeSang, Inc.

InventorSang-Yun Lee

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Abstract

Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

Claims32

Dependent claims

A method of constructing a 3D NVM module, comprising:

providing a substrate;
forming a logic layer on said substrate;
disposing a semiconductor layer over said logic layer;
patterning said semiconductor layer to form semiconductor pillars;
disposing a composite gate dielectric on each of said semiconductor pillars;
disposing a control gate material on said composite gate dielectric;
etching said control gate material anisotropically to form a control gate;
disposing a dielectric layer after forming said control gate;
forming a first set of 3D vias through said dielectric layer;
disposing a first set of metal lines on said dielectric layer over said semiconductor pillars and said first set of 3D vias;
and wherein:
said control gate material is etched with a sufficient over-etch such that said control gate surrounds a middle portion of each of said semiconductor pillars;
each of said first set of metal lines couples respective one or more of said first set of 3D vias to a respective group of said semiconductor pillars that are formed in a respective line along a bit-line direction;
said logic layer comprises a memory control circuit;
and
said first set of 3D vias are coupled to said memory control circuit.

13 more elements

A method of constructing a 3D NVM module, comprising:

providing a substrate;
forming a circuitry on said substrate;
forming underlying bypass vias in a top region of said circuitry;
disposing a conductive layer over said substrate and over said circuitry;
patterning said conductive layer to form semiconductor pillars as bodies of vertical transistors arranged in an array;
disposing a composite gate dielectric on each of said semiconductor pillars;
and
disposing a control gate on said composite gate dielectric so as to surround a middle portion of each of said semiconductor pillars;
disposing bit lines over said vertical transistors;
disposing word lines over said vertical transistors;
and wherein:
said array has a bit-line direction and a word-line direction, perpendicular to each other;
said conductive layer becomes a conductive film after said semiconductor pillars are formed from said conductive layer;
said word lines are coupled to said control gate of said vertical transistors which are respectively arranged along said word-line direction;
said bit lines are coupled to top regions of said vertical transistors which are respectively arranged along said bit-line direction;
a spacing between said vertical transistors along said word-line direction is smaller than a spacing between said vertical transistors along said bit-line direction;
said circuitry comprises planar transistors, dielectric layers, and interconnect layers;
a top horizontal surface of said bypass vias is exposed when said conductive layer is disposed;
and
said conductive layer is couple to said circuitry through said underlying bypass vias.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/347,237Filed 14 Jun 2021 · continuation
Priority: 7 Jun 2021
Published: US 2022/0392910 A18 Dec 2022
Granted: 11 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/20
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by three-dimensional [3D] arrangements, e.g.…

Family

Application17/340,371Parent of this continuation · filed 7 Jun 2021
US 2022/0392910 A1Pre-grant publication · published 8 Dec 2022
US 11,925,026 B2Related patent
US 2022/0392913 A1Published application
US 12,010,853 B2This patent

From the US filing history. Foreign family members aren’t listed.

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