Method and structure for reduce OTP cell area and leakage

A memory device comprising:

• a first memory cell in a first cell row, the first memory cell comprising:
• a first active region extending in a first direction,
• a first continuous polysilicon line over active region edge (“CPODE”);
• a first polysilicon line associated with a first read word line;
• a second polysilicon line associated with a second read word line;
• and
• a third polysilicon line associated with a first program word line;
• and
• a second memory cell in a second cell row, the second memory cell comprising:
• a second active region extending in the first direction;
• a second CPODE;
• a fourth polysilicon line associated with a second program word line;
• a fifth polysilicon line associated with a third read word line;
• and
• a sixth polysilicon line associated with a fourth read word line,
• wherein the first cell is shifted in the first direction relative to the second cell.

A memory device comprising:

• a first memory cell in a first cell row, the first memory cell comprising:
• a first active region extending in a first direction,
• a first continuous polysilicon line over active region edge (“CPODE”);
• a first polysilicon line associated with a first read word line;
• a second polysilicon line associated with a second read word line;
• and
• a third polysilicon line associated with a first program word line;
• and
• a second memory cell in a second cell row, the second memory cell comprising:
• a second active region extending in the first direction;
• a second CPODE;
• a fourth polysilicon line associated with a second program word line;
• a fifth polysilicon line associated with a third read word line;
• and
• a sixth polysilicon line associated with a fourth read word line,
• wherein either the first cell or the second cell is shifted by at least one polysilicon line pitch with respect to the second cell or the first cell, respectively.