3D DRAM with multiple memory tiers and vertically extending digit lines

An integrated assembly, comprising:

• a memory array over a base;
• the memory array comprising a three-dimensional arrangement of memory cells;
• sense amplifiers associated with the base and being directly under the memory array;
• vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
• a channel region between the source/drain regions and comprising at least two sides, a gate region operatedly adjacent only one side of the channel region;
• wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
• and
• wherein the memory array includes 128 vertically-stacked tiers of the memory cells and wherein the memory array comprises 128 wordlines associated with each of the individual tiers of the memory cells.

An integrated assembly, comprising:

• a memory array over a base;
• the memory array comprising a three-dimensional arrangement of memory cells;
• sense amplifiers associated with the base and being directly under the memory array;
• vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
• wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
• and
• wherein the vertically-extending digit lines extend directly through source/drain regions of transistors in the memory cells.

An integrated assembly, comprising:

• a memory array over a base;
• the memory array comprising a three-dimensional arrangement of memory cells;
• sense amplifiers associated with the base and being directly under the memory array;
• vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
• wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
• a conductive plate extending vertically along the three-dimensional arrangement of memory cells;
• and
• storage elements coupled with the memory cells, the storage elements being separate structures from the conductive plate.

An integrated assembly, comprising:

• a memory array over a base;
• the memory array comprising a three-dimensional arrangement of memory cells;
• sense amplifiers associated with the base and being directly under the memory array;
• vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
• wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
• and
• wherein an entirety of the structure for the vertically-extending digit lines extend only vertically.

An integrated assembly, comprising:

• a memory array over a base;
• the memory array comprising a three-dimensional arrangement of memory cells;
• sense amplifiers associated with the base and being directly under the memory array;
• vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
• wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
• and
• wherein the digit lines are subdivided amongst comparative sets, with each of the comparative sets comprising a first comparative digit line and a second comparative digit line comparatively coupled to the first comparative digit line through one of the sense amplifiers.

An integrated assembly, comprising:

• a memory array over a base;
• the memory array comprising a three-dimensional arrangement of memory cells;
• sense amplifiers associated with the base and being directly under the memory array;
• vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
• a channel region between the source/drain regions and comprising at least two sides, a gate region operatedly adjacent only one side of the channel region;
• wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
• wherein the memory cells include horizontally-extending access devices coupled with storage elements;
• and
• wherein the memory array includes 128 vertically-stacked tiers of the memory cells and wherein the memory array comprises 128 wordlines associated with each of the individual tiers of the memory cells.