Memory-efficient hardware cryptographic engine

An electronic apparatus comprising a hardware cryptographic engine and a memory bus, wherein the hardware cryptographic engine comprises:

• a direct-memory-access input module for receiving input data over the memory bus;
• and
• a cryptographic module,
• wherein the cryptographic module comprises:
• an input register having an input-register length;
• and
• circuitry configured to perform a cryptographic operation on data in the input register,
• wherein the hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and hardware alignment circuitry for performing an alignment operation on input data in the input-alignment buffer;
• and
• wherein the hardware cryptographic engine is configured to pass input data, received by the direct-memory-access input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.

A method of performing a cryptographic operation on data, the method comprising:

• receiving input data by direct memory access over a memory bus;
• and
• performing a cryptographic operation on the received input data using a hardware cryptographic module that comprises an input register having an input-register length and circuitry configured to perform the cryptographic operation on data in the input register, wherein the method comprises:
• buffering the input data, received over the memory bus, in an input-alignment buffer having a length that is less than twice said input-register length;
• performing, by hardware alignment circuitry, an alignment operation on the input data in the input-alignment buffer;
• and
• passing the input data to the input register of the cryptographic module after buffering an amount of the input data no greater than the length of the input-alignment buffer.