US 12,009,843 B2 · Matrix compression accelerator system and method

Abstract

A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.

Claims16

Dependent claims

A system comprising:

a first memory;
a second memory;
and
a matrix compression accelerator coupled to the first and second memories, wherein the matrix compression accelerator is configured to:
receive 2D uncompressed data from the first memory, wherein the 2D uncompressed data includes a first set of data blocks;
transform the 2D uncompressed data to 1D uncompressed data that includes a second set of data blocks that is a subset of the first set of data blocks of the 2D uncompressed data, wherein the second set of data blocks is not contiguous in the 2D uncompressed data and is contiguous in the 1D uncompressed data;
compressing at least a subset of the 1D uncompressed data to generate a compressed superblock;
and
storing the compressed superblock in the second memory.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/195,703Filed 9 Mar 2021 · continuation

Priority

24 Feb 2017

Published

US 2021/0194498 A124 Jun 2021

Granted

11 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H03M 7/30
Conversion of a code where information is represented by a given sequence or number of digits to a code where the same , similar or subset of…:…
G06F 13/28
For access to input/output bus: using burst mode transfer, e.g. direct memory access DMA, cycle steal
G06F 17/16
Complex mathematical operations: matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
G06N 3/0464
Architecture, e.g. interconnection topology: convolutional networks [CNN, ConvNet]

Family

Application62/463,426Us provisional application · filed 24 Feb 2017

Application62/464,954Us provisional application · filed 28 Feb 2017

Application62/464,964Us provisional application · filed 28 Feb 2017

Application62/465,620Us provisional application · filed 1 Mar 2017

Application15/900,611Parent of this continuation · filed 20 Feb 2018

Application16/899,632Parent of this continuation · filed 12 Jun 2020

US 10,735,023 B2Parent of this continuation · filed 15 Jul 2020

US 2021/0194498 A1Pre-grant publication · published 24 Jun 2021

US 10,979,070 B2Parent of this continuation

US 2018/0248562 A1Published application

US 2020/0304141 A1Published application

US 12,009,843 B2This patent

From the US filing history. Foreign family members aren’t listed.

Matrix compression accelerator system and method

Life of this patent

Matrix compression accelerator system and method

Life of this patent

Abstract

Claims16