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US 12,009,842 B2Granted
Error correcting code circuitry compatible with multi-width interfaces
AssigneeIntel Corporation
InventorQiang Wang
Life of this patent
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Abstract
Systems and methods described herein may relate to providing a dynamically configurable error correction code (ECC) circuitry able to process data having one of a variety of widths. This multi-width ECC circuitry may generate error correction code bits (ECC bits) using, for example, an encoder or a decoder characterized by a fixed data width. Translation circuitry (e.g., a format converter) may translate data received from data utilization circuitry between a data width used by the data utilization circuitry and the fixed data width used by the encoder or the decoder.
Claims19
An integrated circuit, comprising:
- data utilization circuitry configurable to generate first data characterized by a first data width;
- and
- configurable error correction code (ECC) circuitry communicatively coupled between the data utilization circuitry and a memory comprising a memory interface, wherein the configurable ECC circuitry comprises an encoder having a second data width, and wherein the configurable ECC circuitry is configurable to:
- receive the first data from the data utilization circuitry;
- adjust the first data characterized by the first data width into second data characterized by the second data width configurable to be processed by the encoder to generate ECC bits before being stored in the memory, wherein the encoder is configurable to generate the ECC bits based on a logarithmic relationship between the first data width and the second data width;
- process, via an output format converter, the ECC bits to pad the ECC bits with one or more dummy ECC bits to match a width of the ECC bits padded by the one or more dummy ECC bits to a width of the memory interface;
- and
- write the ECC bits padded by the one or more dummy ECC bits to the memory.
5 more elements
A method, comprising:
- receiving first input data characterized by a first data width;
- adjusting the first input data into second data characterized by a second data width;
- generating error correction code (ECC) bits characterized by a third data width using an encoder characterized by the second data width, wherein the ECC bits are generated based on a logarithmic relationship between the third data width and the second data width;
- processing, via an output format converter configurable to couple to a memory via a memory interface characterized by a fourth data width, the ECC bits to pad the ECC bits with one or more dummy ECC bits to match the fourth data width;
- and
- writing the ECC bits padded by the one or more dummy ECC bits to the memory via the memory interface.
3 more elements
A device comprising:
- a format converter communicatively coupled to a memory via a memory interface having a first data width;
- and
- encoding circuitry comprising an input characterized by a second data width communicatively coupled to the format converter, wherein the encoding circuitry is configurable to receive input data having a third data width padded to the second data width and to generate first data having a fourth data width;
- wherein the format converter is configurable to:
- receive the first data characterized by the fourth data width from the encoding circuitry, wherein the first data comprises error correction code (ECC) bits generated by the encoding circuitry, wherein the first data is generated based on a logarithmic relationship between the fourth data width and the second data width;
- generate second data at least in part by padding the first data with one or more dummy ECC bits, wherein the second data is characterized by the first data width;
- and
- write the second data to the memory via the memory interface.
5 more elements
Dependencies are inferred from the claim text.