Command address fault detection

A system, comprising:

• a host device configured to:
• generate a plurality of bits associated with a command signal or an address signal;
• transmit the plurality of bits to a memory device via a command address bus,
• wherein the command address bus is configured for communicating command signals and address signals between the memory device and the host device;
• generate a first set of parity bits based on applying a parity generation process to the plurality of bits that are transmitted via the command address bus;
• receive a second set of parity bits from the memory device;
• and
• compare the first set of parity bits and the second set of parity bits;
• and
• the memory device, wherein the memory device is configured to:
• receive, from the host device via the command address bus, the plurality of bits;
• generate the second set of parity bits based on applying the parity generation process to the plurality of bits that are received via the command address bus;
• and
• transmit, to the host device, the second set of parity bits.

A method performed by a memory device, comprising:

• receiving, from a host device via a command address bus, a plurality of bits associated with a command signal or an address signal,
• wherein the command address bus is configured for communicating command signals and address signals between the memory device and the host device;
• generating one or more parity bits based on applying a parity generation process to the plurality of bits that are received via the command address bus;
• and
• transmitting, to the host device via a parity pin, the one or more parity bits.