Monitor circuitry for power management and transistor aging tracking
AssigneeIntel Corporation
InventorsKuan-Yueh Shen, Nasser A. Kurd, John Fallin
Life of this patent
Estimating the term…
Abstract
Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
Claims11
An apparatus comprising:
- a first circuit on a die;
- and
- a delay locked loop coupled to the first circuit, the delay locked loop including a first circuit path on the die, the first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector;
- a delay line included in the delay locked loop, the delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit;
- a second circuit path included in the delay locked loop and coupled between the delay line and the second input node of the phase frequency detector;
- and
- an analog-to-digital converter coupled to the circuit node.
An apparatus comprising:
- a processor including a processing circuitry and a delay locked loop coupled to the processing circuitry, the processing circuitry including a logic circuit path, the logic circuit path including a first circuit coupled to the delay locked loop, the delay locked loop including:
- a first circuit path including a phase frequency detector having a first input node to receive a first signal, and a circuit node to provide a voltage based on a comparison between the first signal at the first input node of the phase frequency detector and a second signal at a second input node of the phase frequency detector;
- a delay line including an input node to receive the first signal and an output node to provide the second signal having a frequency based on a frequency of the first signal, the delay line including a second circuit coupled to the circuit node, the second circuit including a replica of the first circuit;
- and
- a second circuit path coupled between the delay line and the second input node of the phase frequency detector.
Dependencies are inferred from the claim text.