US 12,009,824 B2 · Clock gating circuit and method of operating the same

Abstract

A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Claims20

Dependent claims

A clock gating circuit comprising:

a NOR logic gate coupled to a first node, and being configured to receive a first enable signal and a second enable signal, and to output a first control signal;
a transmission gate coupled between the first node and a second node, the transmission gate being configured to receive the first control signal, an inverted clock input signal and a clock output signal;
a cross-coupled pair of transistors coupled between the second node and an output node, and being configured to receive at least a second control signal;
and
a first transistor of a first type, the first transistor including a first gate terminal, a first drain terminal and a first source terminal, the first gate terminal being configured to receive the inverted clock input signal, the first drain terminal being coupled to at least the output node, and the first source terminal being coupled to a reference voltage supply, the first transistor being configured to adjust the clock output signal responsive to the inverted clock input signal.

2 more elements

A clock gating circuit comprising:

a NOR logic gate coupled to a first node, and being configured to receive a first enable signal and a second enable signal, and to set a first control signal in response to the first enable signal or the second enable signal;
a transmission gate coupled to the NOR logic gate by the first node, and being further coupled between the first node and a second node, the transmission gate being configured to receive at least the first control signal, an inverted clock input signal or a clock output signal;
a cross-coupled pair of transistors coupled between the second node and an output node, and being configured to receive at least a second control signal or the clock output signal;
and
a first pull-up transistor of a first type, the first pull-up transistor including a first gate terminal, a first drain terminal and a first source terminal, the first gate terminal being configured to receive the inverted clock input signal, the first drain terminal being coupled to at least a third node, and the first source terminal being coupled to a voltage supply, the first pull-up transistor being configured to adjust the clock output signal responsive to the inverted clock input signal.

2 more elements

A method of operating a circuit, the method comprising:

disabling a clock gating circuit in response to at least a first enable signal or a second enable signal, wherein disabling the clock gating circuit comprises:
generating a first control signal;
enabling, by a transmission gate, a first path between a first node and a second node in response to at least an inverted clock input signal or an output clock signal;
disabling, by a first transistor, a second path between a third node and a fourth node in response to a second control signal;
enabling, by at least a second transistor, a third path between the second node and the third node in response to at least the second control signal;
and
setting, by a third transistor, the output clock signal in response to at least the second control signal;
and
outputting, by the fourth node, the output clock signal in response to at least the first enable signal, or the second control signal,
wherein a clock input signal does not correspond to the output clock signal.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/065,327Filed 13 Dec 2022 · division

Priority

17 Jan 2020

Published

US 2023/0110352 A113 Apr 2023

Granted

11 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03K 3/037
By the use of logic circuits, with internal or external positive feedback: bistable circuits
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
H03K 19/20
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: characterised by logic function, e.g. AND, OR, NOR, NOT…

Family

Application62/962,817Us provisional application · filed 17 Jan 2020

Application17/095,191Parent of this division · filed 11 Nov 2020

US 2023/0110352 A1Pre-grant publication · published 13 Apr 2023

US 11,545,965 B2Parent of this division

US 11,870,441 B2Related patent

US 2021/0226615 A1Published application

US 12,009,824 B2This patent

From the US filing history. Foreign family members aren’t listed.

Clock gating circuit and method of operating the same

Life of this patent

Clock gating circuit and method of operating the same

Life of this patent

Abstract

Claims20