Flip-flop circuit, semiconductor integrated circuit device, and vehicle

A flip-flop circuit comprising:

• a master latch including a first inverter and a first tri-state inverter configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor configured such that an inverted clock signal, which is an inversion of the clock signal, is input to the first PMOS transistor;
• a slave latch including a second inverter and a second tri-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter includes a second PMOS transistor configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor configured such that the inverted clock signal is input to the second NMOS transistor;
• and
• at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor,
• wherein the first tri-state inverter further includes two NMOS transistors directly connected to each other and configured such that output of the first inverter is input to gates of the two NMOS transistors.