Slew rate control for fast switching output stages

A system comprising:

• a first power transistor comprising a control terminal;
• a circuit configured to drive operation of the first power transistor, the circuit comprising:
• a replica transistor configured as a replica of the first power transistor, wherein the replica semiconductor is of the same type as the first power semiconductor and wherein the replica semiconductor and the first power semiconductor were fabricated on a same substrate under same conditions;
• a first regulation loop configured to set and maintain a first voltage at a regulated node, wherein the regulation loop comprises the replica transistor;
• a first buffer configured to apply the first voltage from the regulated node to the control terminal of the first power transistor while the first buffer is switched ON;
• and
• a second buffer configured to apply a second voltage to the control terminal while the first buffer is switched OFF;
• a second power transistor;
• and
• a second circuit configured to drive operation of the second power transistor, the second circuit comprising:
• a second replica transistor configured as a replica of the second power transistor;
• a second regulation loop configured to set and maintain a third voltage at a regulated node of the second circuit, wherein the regulation loop comprises the second transistor;
• a third buffer configured to apply the third voltage from the regulated node of the second circuit to the control terminal of the second power transistor while the third buffer is switched ON;
• and
• a fourth buffer configured to apply a fourth voltage to the control terminal of the second power transistor while the third buffer is switched OFF;
• and
• control circuitry configured to manage the operation of the system.

A method comprising:

• regulating a first voltage at a first reference node of a circuit,
• wherein the circuit is configured to drive operation of a power transistor,
• wherein the power transistor comprises a control terminal,
• wherein a regulation loop of the circuit is configured set and maintain the first voltage at the first reference node, and
• wherein the regulation loop comprises a transistor configured as a replica of the power transistor, wherein the replica semiconductor is of the same type as the power semiconductor and wherein the replica semiconductor and the power semiconductor were fabricated on a same substrate under same conditions;
• controlling, by switching control circuitry, the operation of a first buffer with a first enable signal connected to the first buffer, wherein the first buffer connects the first reference node to the control terminal of the power transistor when the first buffer is enabled;
• controlling, by the switching control circuitry, the operation of a second buffer with a second enable signal connected to the second buffer, wherein the second buffer connects a second voltage to the control terminal of the power transistor when the second buffer is enabled;
• in response to receiving the first enable signal at the first buffer, applying the voltage of the reference node to the control terminal of the power transistor;
• and
• generating, by the switching control circuitry, a gate-profile waveform at the control terminal of the power transistor, wherein generating the gate-profile waveform comprises:
• enabling, by the switching control circuitry, the first buffer for a first duration;
• and
• enabling, by the switching control circuitry, a third buffer for a second duration separate from the first duration, wherein enabling the third buffer applies a voltage at a second reference node to the control terminal of the power transistor.