Increasing power efficiency in a digital feedback class D driver
AssigneeAnalog Devices, Inc.
InventorAbhishek Bandyopadhyay
Life of this patent
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Abstract
Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.
Claims20
An architecture for a class D driver, comprising:
- a first summer configured to receive a digital input signal;
- a digital modulator configured to receive a summer output from the first summer and further configured to produce an output;
- and
- an analog feedback loop from a driver output line to the first summer, the analog feedback loop including:
- an analog-to-digital converter comprising a loop filter and a first quantizer, and
- a second summer configured to add an analog-to-digital converter output and a second digital input signal, wherein a second summer output is input to the first summer.
A method for a digital class D driver, comprising:
- receiving a digital input signal at a first summer;
- performing digital modulation on a first summer output from the first summer, at a digital modulator;
- amplifying a digital modulator output at a power stage and generating a driver output signal;
- filtering an error signal from the driver output signal through an analog feedback loop from a driver output line to the first summer, resulting in a filtered signal;
- quantizing the filtered signal at a first quantizer in the analog feedback loop, resulting in a quantized filtered signal;
- adding the quantized filtered signal and a second digital input signal at a second summer to generate a second summer summed signal;
- and
- subtracting, at the first summer, the second summer summed signal from the digital input signal.
A circuit for a digital class D driver, the circuit comprising:
- a first summer configured to receive a digital input signal;
- a digital modulator configured to receive a summer output from the first summer and is further configured to produce a digital modulator output;
- means for amplifying the digital modulator output and generating a driver output signal;
- and
- an analog feedback loop from a driver output line to the first summer, the analog feedback loop including:
- means for filtering an error signal from the driver output signal through the analog feedback loop from the driver output line to the first summer, wherein the analog feedback loop includes an analog-to-digital converter;
- and
- means for adding an analog-to-digital converter output and a second digital input signal to generate a summed feedback signal, wherein the summed feedback signal is input to the first summer.
Dependencies are inferred from the claim text.