In-transistor load modulation

A power amplifier, comprising:

• a semiconductor die comprising a main amplifier including a first transistor, and a peaking amplifier including a second transistor having at least one characteristic different than the first transistor,
• wherein the peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors,
• wherein the semiconductor die further comprises an input transmission line that electrically connects respective inputs of the main and the peaking amplifiers on the semiconductor die to provide an input signal thereto, and an output transmission line that electrically connects respective outputs of the main and the peaking amplifiers on the semiconductor die,
• wherein the respective gates of the first and second transistors comprise respective elongated gate fingers, and wherein the input transmission line comprises a gate runner that electrically connects the respective elongated gate fingers of the first and second transistors to provide the common gate bias thereto, and
• wherein at least one of the input transmission line or the output transmission line comprises an electrical length that is configured to provide signals to the respective inputs or signals from the respective outputs, respectively, with a predetermined phase shift therebetween based on a frequency component of the input signal.

A power amplifier, comprising:

• a semiconductor die comprising a main amplifier including a first transistor having a first threshold voltage, and a peaking amplifier including a second transistor having a second threshold voltage that is different than the first threshold voltage,
• wherein the peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors,
• wherein, based on the common gate bias, the first and second transistors on the semiconductor die are configured to turn on in sequence responsive to different power levels of an input signal to the power amplifier, and
• wherein the semiconductor die further comprises a third amplifier including a third transistor having a third threshold voltage that is different than the first and second threshold voltages.

A method of fabricating a power amplifier, the method comprising:

• forming a semiconductor die comprising a main amplifier including a first transistor and a peaking amplifier including a second transistor having at least one characteristic different than the first transistor,
• wherein the peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors of the semiconductor die,
• wherein the semiconductor die further comprises a transmission line that electrically connects respective inputs or respective outputs of the main amplifier and the peaking amplifier,
• wherein the transmission line comprises a conductive segment extending on the semiconductor die, and a length of the conductive segment extending on the semiconductor die is configured to provide signals to the respective inputs or signals from the respective outputs with a predetermined phase shift therebetween based on a frequency component of an input signal.

A semiconductor device, comprising:

• a semiconductor die;
• a first amplifier on the semiconductor die, the first amplifier comprising a plurality of first transistors having a first threshold voltage and comprising first gate fingers;
• a second amplifier on the semiconductor die, the second amplifier comprising a plurality of second transistors having a second threshold voltage different than the first threshold voltage and comprising second gate fingers;
• and
• a gate runner on the semiconductor die, the gate runner electrically connecting the first gate fingers and the second gate fingers to apply a common gate bias to the first and second amplifiers,
• wherein a portion of the gate runner extending between the first gate fingers and the second gate fingers comprises an electrical length that is based on a frequency component of a radio frequency (RF) input signal to the first and second amplifiers.