Switching power converter with reduced voltage switching of the primary switch

A controller for a switching power converter, the controller comprising:

• a primary-drive terminal, a secondary-drive terminal, a sense terminal, and a feedback terminal;
• a primary controller coupled to the primary-drive terminal and the feedback terminal, the primary controller configured to assert the primary-drive terminal in a charge mode of a first switching period;
• a secondary controller coupled to the secondary-drive terminal, the secondary controller configured to assert the secondary-drive terminal during a discharge mode in the first switching period;
• a modulation controller configured to:
• sense a signal indicative of negative current flow by way of the sense terminal during the first switching period;
• and
• adjust a duration of assertion of the secondary-drive terminal during a second switching period subsequent to the first switching period, the adjustment responsive to the signal indicative of negative current flow during the first switching period,
• wherein the second switching period begins after the first switching period ends.

A switching power converter comprising:

• a primary circuit comprising:
• a primary winding of a transformer, the primary winding having a first terminal coupled to an input node, and a second terminal defining a switch node;
• a primary field effect transistor (primary FET) coupled between the switch node and a ground or common of the primary circuit;
• a clamp diode in series with a clamp capacitor, the clamp diode and clamp capacitor coupled between the input node and the switch node;
• a secondary circuit comprising:
• a secondary winding of the transformer arranged for flyback operation;
• and
• a secondary FET coupled between a terminal of the secondary winding and ground or common of the secondary circuit;
• a controller defining a main drive output coupled to a gate of the primary FET, a second drive output coupled to a gate of the secondary FET, and a sense input coupled to a signal indicative of voltage at the switch node;
• the controller is configured to:
• assert a gate of the primary FET during a charge mode of a first switching period;
• and then
• assert a gate of the secondary FET during a discharge mode of the first switching period;
• sense a signal indicative of negative current flow by way of the sense input during the first switching period;
• and
• adjust a duration of assertion of the gate of the secondary FET during a discharge mode of a second switching period subsequent to the first switching period, the adjustment responsive to the signal indicative of negative current flow during the first switching period,
• wherein the second switching period begins after the first switching period ends.