Charge pump with fractional negative voltage output

A fractional negative voltage charge pump including:

• (a) a first switch comprising a first pair of PFET and NFET transistors having respective conduction channels coupled in series between an input voltage terminal and a ground terminal, and having a first mid-point node located between the first pair of transistors;
• (b) a second switch comprising a second pair of PFET and NFET transistors having respective conduction channels coupled in series between a mid-voltage terminal and a negative voltage output terminal, and having a second mid-point node located between the second pair of transistors;
• (c) a third switch comprising a third pair of PFET and NFET transistors having respective conduction channels coupled in series between the mid-voltage terminal and the ground terminal, and having a third mid-point node located between the third pair of transistors;
• (d) a fourth switch comprising a fourth pair of PFET and NFET transistors having respective conduction channels coupled in series between the ground terminal and the negative voltage output terminal, and having a fourth mid-point node located between the fourth pair of transistors;
• (e) a first capacitor having:
• (1) a first terminal coupled to the first mid-point node and switchably connectable through the first switch to the input voltage terminal during a charging phase and to the ground terminal during a discharging phase;
• and
• (2) a second terminal coupled to the second mid-point node and switchably connectable through the second switch to the mid-voltage terminal during the charging phase and to the negative voltage output terminal during the discharging phase;
• (f) a second capacitor having:
• (1) a first terminal coupled to the third mid-point node and switchably connectable through the third switch to the mid-voltage terminal during the charging phase and to the ground terminal during the discharging phase;
• and
• (2) a second terminal coupled to the fourth mid-point node and switchably connectable through the fourth switch to the ground terminal during the charging phase and to the negative voltage output terminal during the discharging phase;
• (g) a clock generation circuit coupled to the first, second, third, and fourth switches and configured to output an NFET clock signal and a PFET clock signal to respective PFET and NFET transistors of the first, second, third, and fourth switches, wherein the NFET and PFET clock signals are complementary and essentially non-overlapping;
• (h) a first differential clock translator circuit coupled to the second switch and configured to provide level shifting for the respective NFET and PFET clock signals coupled to the second switch;
• (i) the first differential clock translator circuit coupled to the third switch and configured to provide level shifting for the and PFET clock signal coupled to the third switch;
• and
• (j) a third differential clock translator circuit coupled to the fourth switch and configured to provide level shifting for the and PFET clock signal coupled to the fourth switch.