Multi-dielectric gate stack for crystalline thin film transistors

A method of forming a thin film transistor, comprising:

• forming a gate electrode over a substrate;
• forming a gate dielectric stack over the gate electrode, wherein the gate dielectric stack comprises a first layer of HfO2 in direct contact with the gate electrode, a layer of Al2O3 on the first layer of HfO2, and a second layer of HfO2 on the layer of Al2O3, and wherein a first layer of the gate dielectric stack has a first thickness, and a second layer of the dielectric stack has a second thickness different than the first thickness;
• forming a semiconductor layer over the gate dielectric stack, wherein the semiconductor layer comprises a crystalline semiconductor layer in direct contact with the second layer of HfO2 of the gate dielectric stack;
• and
• forming a source electrode and a drain electrode directly on the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the gate dielectric stack.

A computing device, comprising:

• an integrated circuit die, wherein the integrated circuit die comprises a thin film transistor, wherein the thin film transistor comprises:
• a substrate;
• a gate electrode over the substrate;
• an amorphous gate dielectric over the gate electrode, wherein the amorphous gate dielectric comprises a plurality of layers, the plurality of layers comprising a first layer of HfO2 in direct contact with the gate electrode, a layer of Al2O3 on the first layer of HfO2, and a second layer of HfO2 on the layer of Al2O3, and wherein a first layer of the amorphous gate dielectric has a first thickness, and a second layer of the amorphous gate dielectric has a second thickness different than the first thickness;
• a crystalline semiconductor layer over and in direct contact with the second layer of HfO2 of the amorphous gate dielectric;
• and
• a source electrode and a drain electrode, both the source electrode and the drain electrode directly on and in contact with the crystalline semiconductor layer, wherein the gate electrode extends laterally at least as wide as the semiconductor layer and at least as wide as the amorphous gate dielectric.