Semiconductor device and method

A device comprising:

• a gate structure on a substrate;
• a gate spacer adjacent the gate structure;
• a source/drain region adjacent the gate spacer;
• a silicide on the source/drain region, the silicide contacting a sidewall of the gate spacer;
• a source/drain contact on the silicide, the source/drain contact contacting the sidewall of the gate spacer;
• an inter-layer dielectric on a lower portion of the source/drain contact, the inter-layer dielectric surrounding an upper portion of the source/drain contact;
• and
• a void exposing a surface of the inter-layer dielectric, a bottom surface of the source/drain region, and a surface of the silicide.

A device comprising:

• a semiconductor fin;
• a source/drain region in the semiconductor fin, the source/drain region having facets which extend laterally outward beyond sidewalls of the semiconductor fin;
• a dielectric layer on the source/drain region;
• an inter-layer dielectric on the dielectric layer, the dielectric layer comprising a different dielectric material than the inter-layer dielectric;
• a source/drain contact having a main portion extending through the inter-layer dielectric and the dielectric layer and having an undercut portion beneath the inter-layer dielectric, the source/drain contact coupled to the source/drain region, the dielectric layer separated from a sidewall of the source/drain contact by an air gap;
• and
• a silicide between the source/drain contact and the source/drain region, the silicide extending along the facets of the source/drain region.