Semiconductor device and manufacturing method thereof

A semiconductor device, comprising:

• a fin structure extending in a first direction disposed over a substrate, the fin structure including a well layer, an oxide layer disposed over the well layer, and a channel layer disposed over the oxide layer;
• a gate structure extending in a second direction crossing over the fin structure;
• and
• source/drain regions disposed in the fin structure on opposing sides of the gate structure, wherein the source/drain regions comprise:
• a first epitaxial layer;
• a second epitaxial layer disposed over the first epitaxial layer;
• a third epitaxial layer disposed over the second epitaxial layer;
• and
• a fourth epitaxial layer disposed over the third epitaxial layer,
• wherein immediately adjacent epitaxial layers have different compositions;
• and
• a dielectric layer comprising a first portion and a second portion,
• wherein the first portion is disposed in contact with the oxide layer, the well layer, the first epitaxial layer, and the second epitaxial layer, and the second portion is disposed in contact with the fourth epitaxial layer.

A semiconductor device, comprising:

• a fin structure extending in a first direction disposed over a substrate, the fin structure including a well layer, an oxide layer disposed over the well layer, and a channel layer disposed over the oxide layer;
• a gate dielectric layer disposed over the channel layer;
• a gate electrode layer disposed over the gate dielectric layer,
• wherein the gate dielectric layer and the gate electrode layer extend in a second direction crossing the first direction;
• and
• source/drain regions disposed in the fin structure on opposing sides of the channel layer,
• wherein the source/drain regions comprise:
• a first epitaxial layer;
• a second epitaxial layer disposed over the first epitaxial layer;
• a third epitaxial layer disposed over the second epitaxial layer;
• a fourth epitaxial layer disposed over the third epitaxial layer,
• wherein immediately adjacent epitaxial layers have different compositions, and
• wherein an upper surface of the third epitaxial layer is below a level of a lower surface of the gate electrode layer, and an upper surface of the fourth epitaxial layer is above a level of an upper surface the channel layer;
• a dielectric layer disposed between the oxide layer, the well layer, the first epitaxial layer, and the second epitaxial layer,
• a level of an upper surface of the dielectric layer is below a level of a lower surface of the channel layer, and
• the oxide layer and the dielectric layer have different compositions.