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US 12,009,422 B2Granted
Self aligned top contact for vertical transistor
AssigneeInternational Business Machines Corporation
InventorsChoongHyun Lee, Christopher J. Waskiewicz, Chanro Park, Alexander Reznicek
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Abstract
A semiconductor structure including a bottom source drain region arranged on a substrate; a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region; a metal gate disposed around the semiconductor channel region; a top source drain region above the semiconductor channel region; and a top contact partially embedded into the top source drain region.
Claims20
A semiconductor structure comprising:
- a bottom source drain region arranged on a substrate;
- a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
- a metal gate disposed around the semiconductor channel region;
- a top source drain region above the semiconductor channel region;
- and
- a top contact partially embedded into the top source drain region
- a dielectric spacer separating the metal gate from the top source drain region, wherein a width of the dielectric spacer is substantially equal to a width of the top source drain region.
4 more elements
A semiconductor structure comprising:
- a bottom source drain region arranged on a substrate;
- a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
- a metal gate disposed around the semiconductor channel region;
- a top source drain region above the semiconductor channel region;
- a top contact partially embedded into the top source drain region, wherein sidewalls of the top contact are flush or substantially flush with sidewalls of the channel region;
- and
- a gate liner separating the metal gate and the top source drain from an interlevel dielectric layer, wherein an uppermost surface of the gate liner is substantially flush with an uppermost surface of the top source drain region.
4 more elements
A method comprising:
- forming a bottom source drain region arranged on a substrate;
- forming a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
- forming a metal gate disposed around the semiconductor channel region;
- forming a dielectric spacer on the metal gate;
- forming a top source drain region above the semiconductor channel region, wherein the dielectric spacer separates the metal gate from the top source drain region;
- and
- forming a top contact partially embedded into the top source drain region.
4 more elements
Dependencies are inferred from the claim text.