Forming 3D transistors using 2D Van Der Waals materials

A method of manufacturing a semiconductor device, the method comprising:

• forming a dielectric layer;
• forming a dielectric region;
• forming a two-dimensional semiconductor material, wherein a first sidewall of the two-dimensional semiconductor material contacts the dielectric region to form a first vertical interface, wherein the dielectric layer is underlying and in contact with both the dielectric region and the two-dimensional semiconductor material;
• forming a gate dielectric extending on tops of the dielectric region and the two-dimensional semiconductor material, and contacts a second sidewall of the two-dimensional semiconductor material;
• forming a gate electrode on the gate dielectric;
• and
• forming a source/drain contact plug contacting a third sidewall of the two-dimensional semiconductor material to form a second vertical interface, wherein the first sidewall and the third sidewall of the two-dimensional semiconductor material are opposite sidewalls, wherein the source/drain contact plug comprises a bottom surface contacting a top surface of the dielectric layer, wherein after the forming the source/drain contact plug, the source/drain contact plug contacts a top surface of the dielectric region.

A method of manufacturing a semiconductor device, the method comprising:

• forming a dielectric fin;
• forming a transition metal dichalcogenide layer on sidewalls of the dielectric fin, wherein the transition metal dichalcogenide layer comprises a 2D material;
• forming a gate dielectric contacting top surfaces of the dielectric fin, wherein the gate dielectric contacts a first portion of a sidewall of the transition metal dichalcogenide layer;
• forming a gate electrode over the gate dielectric;
• and
• forming a source/drain contact plug contacting a second portion of the sidewall of the transition metal dichalcogenide layer, wherein the source/drain contact plug is free of the 2D material.