Multi-gate devices having a semiconductor layer between an inner spacer and an epitaxial feature
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
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Abstract
The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.
Claims20
A semiconductor device, comprising:
- channel members vertically stacked over a substrate;
- a gate structure engaging the channel members;
- a gate spacer layer disposed on sidewalls of the gate structure;
- an epitaxial feature abutting the channel members;
- an inner spacer layer interposing the gate structure and the epitaxial feature;
- and
- a semiconductor layer interposing the inner spacer layer and the epitaxial feature.
A semiconductor device, comprising:
- one or more channel layers over a substrate;
- a gate structure engaging the one or more channel layers;
- a source/drain (S/D) formation assistance region partially embedded in the substrate, wherein the S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer, and wherein the isolation layer electrically isolates the semiconductor seed layer from the substrate;
- and
- an S/D epitaxial feature connecting to the semiconductor seed layer and the one or more channel layers.
A semiconductor device, comprising:
- channel members vertically stacked over a substrate;
- a gate structure wrapping around each of the channel members;
- an epitaxial feature abutting the channel members;
- an isolation layer in physical contact with the epitaxial feature and the gate structure;
- and
- a semiconductor layer in physical contact with the epitaxial feature and the isolation layer, wherein a top surface and a bottom surface of the semiconductor layer is covered by the isolation layer.
Dependencies are inferred from the claim text.