Semiconductor devices

A semiconductor device comprising:

• a substrate including an active pattern;
• a device isolation layer on the substrate and in a trench that defines the active pattern;
• first, second and third semiconductor patterns that are sequentially stacked on the active pattern and spaced apart from each other in a vertical direction;
• a source/drain pattern connected to the first, second and third semiconductor patterns;
• a first ferroelectric pattern between the active pattern and the first semiconductor pattern, a second ferroelectric pattern between the first semiconductor pattern and the second semiconductor pattern, and a third ferroelectric pattern between the second semiconductor pattern and the third semiconductor pattern;
• a gate electrode on the first, second and third ferroelectric patterns;
• and
• first, second and third inner spacers between the source/drain pattern and the first, second and third ferroelectric patterns, respectively,
• wherein the first, second and third ferroelectric patterns directly contact the first, second and third inner spacers, respectively.

A semiconductor device comprising:

• a substrate including a first active pattern and a second active pattern;
• a device isolation layer on the substrate and in a trench that is between the first and second active patterns;
• a plurality of first semiconductor patterns that are stacked on the first active pattern and spaced apart from each other in a vertical direction;
• a first source/drain pattern connected to the plurality of first semiconductor patterns;
• a plurality of second semiconductor patterns that are stacked on the second active pattern and spaced apart from each other in the vertical direction;
• a second source/drain pattern connected to the plurality of second semiconductor patterns;
• a first ferroelectric pattern on the plurality of first semiconductor patterns;
• a second ferroelectric pattern on the plurality of second semiconductor patterns;
• an inner spacer between the second ferroelectric pattern and the second source/drain pattern;
• a first gate electrode on the first ferroelectric pattern;
• and
• a second gate electrode on the second ferroelectric pattern,
• wherein the first ferroelectric pattern directly contacts the first source/drain pattern, and
• wherein the second ferroelectric pattern is spaced apart from the second source/drain pattern by the inner spacer.