Method of forming a gate structure in high-κ metal gate technology

A method for forming a semiconductor structure comprising:

• forming a gate dielectric structure on a substrate;
• forming a gate electrode structure on the gate dielectric structure;
• forming a sidewall spacer around the gate dielectric structure and the gate electrode structure;
• removing the gate electrode structure to define an opening above the gate dielectric structure;
• depositing a plurality of conductive layers lining the opening, wherein the plurality of conductive layers comprises a first conductive layer stacked with a second conductive layer;
• performing an etching process on the plurality of conductive layers thereby defining a conductive structure over the gate dielectric structure, wherein a top surface of the first conductive layer and a top surface of the second conductive layer define a top surface of the conductive structure, wherein the top surface of the conductive structure is vertically below a top surface of the sidewall spacer;
• depositing a gate body layer on the conductive structure, wherein the gate body layer comprises a lower segment surrounded by the conductive structure and an upper segment contacting the top surface of the conductive structure;
• and
• changing a portion of the upper segment of the gate body layer into a silicide layer, wherein outer sidewalls of the silicide layer are aligned with outer sidewalls of the gate body layer.

A method for manufacturing a semiconductor device comprising:

• forming a dummy gate structure over a semiconductor substrate, wherein the dummy gate structure comprises a high-K gate dielectric structure overlying the semiconductor substrate and further comprises a dummy gate electrode overlying the high-K gate dielectric structure, and wherein a sidewall spacer surrounds the dummy gate structure;
• replacing the dummy gate electrode with a stack of gate electrode layers, wherein the stack of gate electrode layers comprises metal layers and a polysilicon layer overlying the metal layers;
• converting an upper portion of the polysilicon layer into a silicide layer, wherein the silicide layer comprises a lateral segment directly overlying an upper surface of the metal layers and an upper surface of the sidewall spacer;
• and
• performing a planarization process into the stack of gate electrode layers until the upper surface of the sidewall spacer is exposed, thereby defining a gate electrode structure, wherein the planarization process removes the lateral segment.