Device providing multiple threshold voltages and methods of making the same

A method, comprising:

• forming a dielectric layer on a semiconductor workpiece;
• forming a first patterned layer of a first dipole material on the dielectric layer;
• performing a first thermal drive-in operation for a first time duration to drive a subset of the first dipole material into the dielectric layer, thereby forming a remaining portion of the first dipole material and a first intermixing region of the dielectric layer including the first dipole material;
• performing a first etching operation to remove the remaining portion of the first dipole material;
• forming a second patterned layer of a second dipole material on the dielectric layer, a first portion of the second patterned layer being disposed on a first portion of the dielectric layer without the first dipole material and a second portion of the second patterned layer being disposed on a second portion of the dielectric layer with the first dipole material;
• performing a second thermal drive-in operation for a second time duration, thereby forming a remaining portion of the second dipole material, wherein the second time duration is greater than the first time duration;
• and
• performing a second etching operation to remove the remaining portion of the first second dipole material,
• wherein the performing of the first etching operation includes recessing the first intermixing region of the dielectric layer including the first dipole material.

A semiconductor device, comprising:

• a semiconductor substrate;
• a first transistor on the semiconductor substrate having a first channel, a first interfacial layer, a first gate dielectric layer on the first channel, and a first gate electrode layer on and interfacing with the first gate dielectric layer;
• and
• a second transistor on the semiconductor substrate having a second channel, a second interfacial layer, a second gate dielectric layer on the second channel, and a second gate electrode layer on and interfacing with the second gate dielectric layer,
• wherein the first gate electrode layer and the second gate electrode layer have a same composition,
• wherein the first gate dielectric layer includes a first dipole material composition having a maximum concentration at a half-thickness line of the first gate dielectric layer, and
• wherein the second gate dielectric layer includes a second dipole material composition having a maximum concentration at an interface between the second gate dielectric layer and the second interfacial layer.