Self-aligned block for vertical FETs

A semiconductor device comprising:

• a pFET comprising:
• a pFET channel fin between a pFET bottom source/drain (S/D) region and a pFET top S/D region;
• a pFET gate upon around the pFET channel fin, the pFET gate comprising a first pFET gate portion directly connected to a first side of the pFET channel fin and a second pFET gate portion directly connected to a second side of the pFET channel fin, the first pFET gate portion comprising a first pFET gate sidewall and a second pFET gate sidewall, and the second pFET gate portion comprising a third pFET gate sidewall;
• a pFET top metallization upon the pFET top S/D region;
• a pFET contact metallization connected to the pFET bottom S/D region;
• and a pFET vertical liner directly connected the third pFET gate sidewall and directly connected to a sidewall of the pFET contact metallization;
• a nFET comprising:
• a nFET channel fin between a nFET bottom S/D region and a nFET top S/D region;
• a nFET gate around the nFET channel fin, the nFET gate comprising a first nFET gate portion directly connected to a first side of the nFET channel fin and a second nFET gate portion directly connected to a second side of the nFET channel fin, the first nFET gate portion comprising a first nFET gate sidewall and a second nFET gate sidewall, and the second nFET gate portion comprising a third nFET gate sidewall;
• a nFET top metallization upon the nFET top S/D region;
• a nFET contact metallization connected to the nFET bottom S/D region;
• and a nFET vertical liner directly connected a first sidewall of the nFET gate and directly connected to a sidewall of the nFET contact metallization;
• a shared contact metallization connected to the first sidewall of the pFET gate and connected to the first sidewall of the nFET gate;
• a shared vertical liner in direct contact with at least the second sidewall of the pFET gate, in direct contact with the shared contact metallization, and in direct contact with at least the second sidewall of the nFET gate;
• and
• a shared top spacer around the pFET channel around the nFET channel and in direct contact with the shared vertical liner.