Semiconductor device with reduced withstand voltage fluctuations

A semiconductor device comprising:

• a semiconductor chip having a main surface;
• a first conductivity type drift region formed in a surface layer portion of the main surface;
• and
• a second conductivity type column region formed in a column shape extending in a thickness direction in the drift region, the column region having a lower end portion, an intermediate portion and an upper end portion,
• wherein the column region has:
• a lower compensation region including a low concentration portion which is formed between the lower end portion and the intermediate portion and a lower high concentration portion which is formed between the low concentration portion and the lower end portion, the lower compensation region in which a charge balance is compensated within an impurity concentration range between the low concentration portion and the lower high concentration portion;
• an upper compensation region including a high concentration portion which is formed between the intermediate portion and the upper end portion and an upper low concentration portion which is formed between the high concentration portion and the upper end portion, the upper compensation region in which a charge balance is compensated within an impurity concentration range between the high concentration portion and the upper low concentration portion, and
• the upper low concentration portion has a higher concentration than the low concentration portion.