Integrated circuit and method of forming the same

A method of forming an integrated circuit, the method comprising:

• placing, by a processor, a first standard cell layout design of the integrated circuit on a layout design, the first standard cell layout design having a first height, the placing the first standard cell layout design includes:
• placing a first set of pin layout patterns on a first layout level and over a first set of gridlines, the first set of pin layout patterns extending in a first direction, and having a first width in a second direction different from the first direction;
• placing a first set of gate layout patterns on a second layout level different from the first layout level, the first set of gate layout patterns extending in the second direction different from the first direction;
• placing a second standard cell layout design of the integrated circuit adjacent to the first standard cell layout design, the second standard cell layout design having a second height different from the first height, the first height and the second height being in the second direction, the placing the second standard cell layout design includes:
• placing a second set of pin layout patterns on the first layout level and over a second set of gridlines, the second set of pin layout patterns extending in the first direction, and having a second width in the second direction, the second width being different from the first width;
• and
• placing a second set of gate layout patterns on the second layout level, the second set of gate layout patterns extending in the second direction;
• and
• manufacturing the integrated circuit based on at least the first standard cell layout design or the second standard cell layout design.

A system for manufacturing an integrated circuit, the system comprising:

• a non-transitory computer readable medium configured to store non-transitory instructions;
• and
• a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the non-transitory instructions comprising:
• placing a first standard cell layout design of the integrated circuit on a layout design, the first standard cell layout design having a first height, the placing the first standard cell layout design includes:
• placing a first set of pin layout patterns on a first layout level and over a first set of gridlines, the first set of pin layout patterns extending in a first direction, and having a first width in a second direction different from the first direction;
• placing a second standard cell layout design of the integrated circuit adjacent to the first standard cell layout design, the second standard cell layout design having a second height different from the first height, the first height and the second height being in the second direction, the placing the second standard cell layout design includes:
• placing a second set of pin layout patterns on the first layout level and over a second set of gridlines, the second set of pin layout patterns extending in the first direction, and having a second width in the second direction, the second width being different from the first width.