US 12,009,350 B2Granted

Semiconductor package and method of fabricating the same

AssigneeSamsung Electronics Co., Ltd.

InventorsKyoung Lim Suk, Seokhyun Lee

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Abstract

A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

Claims19

Dependent claims

A semiconductor package, comprising:

a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate;
and
a solder ball on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
a first insulating layer;
a redistribution pattern including a via portion in the first insulating layer and an interconnection portion connected to the via portion, the interconnection portion disposed on the first insulating layer;
a seed pattern covering a bottom surface and a side surface of the via portion and extending to a lower surface of the interconnection portion;
and
a second insulating layer on the first insulating layer, the second insulating layer covering side surfaces of the interconnection portion,
wherein the seed pattern does not cover the side surfaces of the interconnection portion,
wherein the seed pattern is provided between the via portion and the solder ball, and
wherein a lowermost surface of the seed pattern is coplanar with a bottom surface of the first insulating layer.

10 more elements

A semiconductor package, comprising:

a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate;
and
a solder ball on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
a first redistribution pattern including a first via portion on the solder ball and a first interconnection portion connected to the first via portion;
a first seed pattern covering a bottom surface and a side surface of the first via portion and extending to a lower surface of the first interconnection portion;
a first insulating layer on an upper surface of the first interconnection portion;
a second redistribution pattern on the first redistribution pattern, the second redistribution pattern including a second via portion in the first insulating layer and a second interconnection portion connected to the second via portion;
a second seed pattern covering a bottom surface and a side surface of the second via portion and extending to a lower surface of the second interconnection portion;
and
a second insulating layer on the first insulating layer, the second insulating layer covering side surfaces of the second interconnection portion,
wherein the first seed pattern does not cover side surfaces of the first interconnection portion,
wherein the second seed pattern does not cover the side surfaces of the second interconnection portion,
wherein the first seed pattern is provided between the first via portion and the solder ball,
wherein a top surface of the second insulating layer is substantially coplanar with a top surface of the second interconnection portion, and
wherein the solder ball is adjacent to a bottom surface of the first seed pattern.

14 more elements

A semiconductor package, comprising:

a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate;
and
a solder ball on a bottom surface of the redistribution substrate,
wherein the redistribution substrate comprises:
a first insulating layer;
a first redistribution pattern including a first via portion in the first insulating layer and a first interconnection portion connected to the first via portion, the first interconnection portion disposed on the first insulating layer;
a first seed pattern covering a bottom surface and a side surface of the first via portion and extending to a lower surface of the first interconnection portion;
a second insulating layer on the first insulating layer, the second insulating layer covering side surfaces of the first interconnection portion and a side surface of the first seed pattern,
a third insulating layer on an upper surface of the first interconnection portion;
a second redistribution pattern on the first redistribution pattern, the second redistribution pattern including a second via portion in the third insulating layer and a second interconnection portion connected to the second via portion;
a second seed pattern covering a bottom surface and a side surface of the second via portion and extending to a lower surface of the second interconnection portion;
and
a fourth insulating layer on the third insulating layer, the fourth insulating layer covering side surfaces of the second interconnection portion and a side surface of the second seed pattern,
wherein the first seed pattern does not cover the side surfaces of the first interconnection portion,
wherein the second seed pattern does not cover the side surfaces of the second interconnection portion,
wherein the first seed pattern is provided between the first via portion and the solder ball, and
wherein the solder ball is adjacent to a bottom surface of the first seed pattern.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/130,760Filed 4 Apr 2023 · continuation
Priority: KR 10-2018-01071247 Sep 2018
Published: US 2023/0245966 A13 Aug 2023
Granted: 11 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification39 codes

H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…
H10W 90/00
Package configurations
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs

Family

Application16/430,426Parent of this continuation · filed 4 Jun 2019
Application17/179,470Parent of this continuation · filed 19 Feb 2021
US 10,930,625 B2Parent of this continuation · filed 23 Feb 2021
US 11,626,393 B2Parent of this continuation · filed 11 Apr 2023
US 2023/0245966 A1Pre-grant publication · published 3 Aug 2023
US 2020/0083201 A1Published application
US 2021/0193636 A1Published application
US 12,009,350 B2This patent

From the US filing history. Foreign family members aren’t listed.

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