US 12,009,344 B2Granted

Semiconductor package including stacked semiconductor chips

AssigneeSK hynix Inc.

InventorJin Kyoung Park

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Abstract

A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.

Claims18

Dependent claims

A semiconductor package comprising:

a base layer;
a chip stack stacked over the base layer, the chip stack includes first to fourth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include chip identification pads;
inter-chip wires connecting the chip identification pads of one semiconductor chip of the chip stack with the chip identification pads of adjacent semiconductor chip of the chip stack;
and
stack wires connecting the chip identification pads of the first semiconductor chip to the base layer,
wherein the chip identification pads include first and second chip identification pads,
wherein each of the first and second chip identification pads of the first semiconductor chip are connected to the base layer via the stack wires,
wherein the inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
wherein the inter-chip wires are configured to supply power to the first semiconductor chip through the first chip identification pad of the first semiconductor chip,
wherein the inter-chip wires are configured to supply power to the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and
wherein the inter-chip wires are configured to supply power to the third semiconductor chip through the second chip identification pad of the third semiconductor chip.

8 more elements

A semiconductor package comprising:

a base layer;
a first chip stack and a second chip stack stacked over the base layer, each of the first and second chip stacks including first to eighth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include stack identification pads and chip identification pads;
first inter-chip wires connecting the chip identification pads of one semiconductor chip of the first chip stack with the chip identification pads of adjacent semiconductor chip of the first chip stack;
first stack wires connecting the chip identification pad of the first semiconductor chip of the first chip stack to the base layer;
second inter-chip wires connecting the chip identification pads of one semiconductor chip of the second chip stack with the chip identification pads of adjacent semiconductor chip of the second chip stack;
and
second stack wires connecting the chip identification pad of the first semiconductor chip of the second chip stack to the base layer,
wherein the chip identification pads include first to third chip identification pads,
wherein the first, second, and third chip identification pads of the first semiconductor chip of the first chip stack are connected to the base layer via the first stack wires, respectively,
wherein, in the first chip stack, the first inter-chip wires connect to two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the selected two chip identification pads of the second semiconductor chip, the selected two chip identification pads of the third semiconductor chip, and the selected two chip identification pads of the fourth semiconductor chip are different from each other, and wherein the selected one chip identification pad of the fifth semiconductor chip, the selected one chip identification pad of the sixth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different from each other,
wherein the first, second, and third chip identification pads of the first semiconductor chip of the second chip stack are connected to the base layer via the second stack wires, respectively,
wherein, in the second chip stack, the second inter-chip wires connect two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the selected two chip identification pads of the second semiconductor chip, the selected two chip identification pads of the third semiconductor chip, and the selected two chip identification pads of the fourth semiconductor chip are different from each other, and wherein the selected one chip identification pad of the fifth semiconductor chip, the selected one chip identification pad of the sixth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different from each other.

9 more elements

A semiconductor package comprising:

a base layer;
a first chip stack and a second chip stack stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include stack identification pads and chip identification pads;
first inter-chip wires connecting the chip identification pads of one semiconductor chip of the first chip stack with the chip identification pads of adjacent semiconductor chip of the first chip stack;
first stack wires connecting the chip identification pad of the first semiconductor chip of the first chip stack to the base layer;
second inter-chip wires connecting the chip identification pads of one semiconductor chip of the second chip stack with the chip identification pads of adjacent semiconductor chip of the second chip stack;
second stack wires connecting the chip identification pad of the first semiconductor chip of the second chip stack to the base layer,
wherein the chip identification pads include first and second chip identification pads,
wherein each of the first and second chip identification pads of the first semiconductor chip of the first chip stack are connected to the base layer via the first stack wires,
wherein, in the first chip stack, the first inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
wherein each of the first and second chip identification pads of the first semiconductor chip of the second chip stack are connected to the base layer via the second stack wires,
wherein, in the second chip stack, the second inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
wherein, in the first chip stack, the first inter-chip wires are configured to supply power to:
the first semiconductor chip through the first chip identification pad of the first semiconductor chip,
the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and
the third semiconductor chip through the second chip identification pad of the third semiconductor chip.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/200,063Filed 12 Mar 2021
Priority: KR 10-2020-017639916 Dec 2020
Published: US 2022/0189924 A116 Jun 2022
Granted: 11 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10W 90/00
Package configurations
H10W 46/00
Marks applied to devices
H10W 46/401
Marks applied to devices, e.g. for alignment or identification: for identification or tracking
H10W 46/403
For identification or tracking: for non-wireless electrical read out

Family

US 2022/0189924 A1Pre-grant publication · published 16 Jun 2022
US 12,009,344 B2This patent

From the US filing history. Foreign family members aren’t listed.

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