Semiconductor device having high yield strength intermediate plate
AssigneeMitsubishi Electric Corporation
InventorsYosuke Nakata, Taishi Sasaki
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Abstract
A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). An intermediate plate (6) is provided in the first solder (2) between the electrode substrate (1) and the semiconductor chip (3). A yield strength of the intermediate plate (6) is higher than yield strengths of the electrode substrate (1) and the first solder (2) within the whole operating temperature range of the semiconductor device.
Claims19
A semiconductor device comprising:
- an electrode substrate;
- a semiconductor chip bonded to an upper surface of the electrode substrate via a first solder;
- a lead frame bonded to an upper surface of the semiconductor chip via a second solder;
- an intermediate plate provided in the first solder between the electrode substrate and the semiconductor chip;
- and
- a plurality of bumps provided between the electrode substrate and the semiconductor chip, the plurality of bumps being comprised of wire,
- wherein a yield strength of the intermediate plate is higher than yield strengths of the electrode substrate and the first solder within the whole operating temperature range of the semiconductor device,
- an outermost periphery of the intermediate plate is positioned inward of an outer periphery of the semiconductor chip and the first solder in planar view,
- the intermediate plate is positioned inward of the plurality of bumps in planar view, and
- the uppermost height of the bumps is less than a total thickness of the first solder, such that the bump does not contact the semiconductor chip.
A semiconductor device comprising:
- an electrode substrate;
- a semiconductor chip bonded to an upper surface of the electrode substrate via a first solder;
- a lead frame directly bonded to an upper surface of the semiconductor chip via a second solder;
- an intermediate plate provided in the first solder between the electrode substrate and the semiconductor chip;
- and
- a plurality of bumps provided between the electrode substrate and the semiconductor chip, the plurality of bumps being comprised of wire,
- wherein a yield strength of the intermediate plate is higher than yield strengths of the electrode substrate and the first solder within the whole operating temperature range of the semiconductor device,
- an outer periphery of the intermediate plate is positioned inward of an outer periphery of the semiconductor chip and the first solder in planar view,
- the intermediate plate is positioned inward of the plurality of bumps in planar view, and
- the uppermost height of the bumps is less than a total thickness of the first solder, such that the bump does not contact the semiconductor chip.
Dependencies are inferred from the claim text.