Semiconductor package and method of manufacturing the same

A semiconductor package, comprising:

• a semiconductor chip including a pad;
• a first insulation pattern on an upper surface of the semiconductor chip and exposing the pad;
• a redistribution layer (RDL) on an upper surface of the first insulation pattern and electrically connected to the pad;
• a second insulation pattern on the upper surface of the first insulation pattern, the second insulation pattern including at least one opening that exposes a ball land of the RDL, and at least one patterned portion located in the opening;
• an under bump metal (UBM) on upper surfaces of the second insulation pattern and the patterned portion and filling the opening, the UBM including a hole and at least one branch that crosses the hole in a radial direction of the UBM;
• and
• a conductive ball on an upper surface of the UBM, the conductive ball including a locking portion in the hole.

A method of manufacturing a semiconductor package, the method comprising:

• forming a first insulation pattern on an upper surface of a semiconductor chip to expose a pad of the semiconductor chip;
• forming a redistribution layer (RDL) on an upper surface of the first insulation pattern, the RDL being electrically connected to the pad;
• forming a second insulation pattern on the upper surface of the first insulation pattern, the second insulation pattern including at least one opening that exposes a ball land of the RDL and including at least one patterned portion located in the opening;
• forming an under bump metal (UBM) on upper surfaces of the second insulation pattern and the patterned portion to fill the opening, the UBM including a hole that exposes the ball land and at least one branch that crosses the hole in a radial direction of the UBM;
• and
• forming a conductive ball on an upper surface of the UBM, the conductive ball including a locking portion inserted into the hole.