US 12,009,327 B2 · Semiconductor die

Abstract

A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.

Claims20

Dependent claims

A semiconductor die, comprising:

a semiconductor substrate,
an interconnect structure disposed on and electrically connected to the semiconductor substrate, the interconnect structure comprising:
stacked interconnect layers, each of the stacked interconnect layers comprising a dielectric layer and an interconnect wiring embedded in the dielectric layer, wherein the interconnect wiring of a first interconnect layer among the stacked interconnect layers further comprises:
a first via electrically connected to the interconnect wiring;
second vias connected to the interconnect wiring, wherein the first via and the second vias are located on a same level height, wherein the second vias are electrically insulated from the first via;
and
a conductive bump disposed on the interconnect structure, wherein the conductive bump comprises a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.

4 more elements

A semiconductor die, comprising:

a semiconductor substrate,
an interconnect structure disposed on and electrically connected to the semiconductor substrate, the interconnect structure comprising:
a first interconnect layer comprising a first dielectric layer, a first interconnect wiring embedded in the first dielectric layer, a first via and second vias;
and
a second interconnect layer disposed on the first interconnect layer, the second interconnect layer comprising a second dielectric layer and a second interconnect wiring embedded in the second dielectric layer, wherein the first via is disposed between the first interconnect wiring and the second interconnect wiring, the first via electrically connects the first interconnect wiring to the second interconnect wiring, and the second vias are disposed between the first interconnect wiring and the second interconnect wiring;
and
an insulating layer and a metallization pattern disposed on the interconnect structure, wherein the metallization pattern is embedded in the insulating layer,
wherein the first dielectric layer is a topmost layer of the interconnect structure, the insulating layer is disposed over the first dielectric layer, and a dielectric constant of the first dielectric layer is less than a dielectric constant of the insulating layer,
wherein the first via and the second vias are embedded in the first dielectric layer, and the first via is spaced apart from the second vias, and the second vias are electrically insulated from the first via.

6 more elements

A semiconductor die, comprising:

a semiconductor substrate,
an interconnect structure disposed on and electrically connected to the semiconductor substrate, the interconnect structure comprising:
a first interconnect layer comprising a first dielectric layer, a first interconnect wiring embedded in the first dielectric layer, a conduction via and at least one stress release via;
and
a second interconnect layer disposed on the first interconnect layer, the second interconnect layer comprising a second dielectric layer and a second interconnect wiring embedded in the second dielectric layer, wherein the conduction via is disposed between the first interconnect wiring and the second interconnect wiring, and the at least one stress release via is disposed between the first interconnect wiring and the second interconnect wiring;
and
a conductive pad disposed on the interconnect structure, wherein the conductive pad is electrically connected to the conduction via,
wherein the conduction via and the at least one stress release via are embedded in the first dielectric layer, and the conduction via is electrically insulated from the at least one stress release via.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor die

Life of this patent

Semiconductor die

Life of this patent

Abstract

Claims20