SRAM bit cells with three-dimensional integration

A method of forming a structure for a static random access memory bitcell, the method comprising:

• forming a first n-type field-effect transistor on a first substrate, wherein the first n-type field-effect transistor includes a first gate;
• forming a second n-type field-effect transistor on the first substrate, wherein the second n-type field-effect transistor includes a second gate;
• forming a first p-type field-effect transistor on a second substrate, wherein the first p-type field-effect transistor includes a first gate;
• forming a second p-type field-effect transistor on the second substrate, wherein the second p-type field-effect transistor includes a second gate and a second source/drain region;
• forming a first interconnect structure on the first substrate, wherein the first interconnect structure includes a first metal feature and a second metal feature, the first metal feature of the first interconnect structure is connected to the first gate of the first n-type field-effect transistor, the second metal feature of the first interconnect structure is connected to the second gate of the second n-type field-effect transistor, the first metal feature includes a first surface, and the second metal feature includes a second surface;
• forming a second interconnect structure on the second substrate, wherein the second interconnect structure includes a first metal feature and a second metal feature, the first metal feature of the second interconnect structure is connected to the first gate of the first p-type field-effect transistor, the second metal feature of the second interconnect structure is connected to the second gate of the second p-type field-effect transistor, the first metal feature of the second interconnect structure includes a first surface that is connected to the first surface of the first metal feature of the first interconnect structure, and the second metal feature of the second interconnect structure includes a second surface that is connected to the second surface of the second metal feature of the first interconnect structure,
• wherein the first metal feature of the second interconnect structure is further connected to the first source/drain region of the first p-type field-effect transistor, and the second metal feature of the second interconnect structure is further connected to the second source/drain region of the second p-type field-effect transistor.