Semiconductor device having a plurality of semiconductor layers covering an emission layer

A semiconductor device comprising:

• a first semiconductor chip having a first semiconductor substrate and a first semiconductor element formed on the first semiconductor substrate;
• a second semiconductor chip having a second semiconductor substrate and a second semiconductor element formed on the second semiconductor substrate;
• a first wiring electrically connected to an anode of the first semiconductor element;
• and
• a second wiring electrically connected to a cathode of the second semiconductor element,
• wherein the first semiconductor element includes:
• a first laminated pattern formed on the first semiconductor substrate, the first laminated pattern including a first end surface, a second end surface opposite the first end surface, a first side surface located between the first end surface and the second end surface, a second side surface located between the first end surface and the second end surface and opposite to the first side surface, and a first upper surface;
• a first semiconductor layer covering the first side surface of the first laminated pattern;
• a second semiconductor layer covering the second side surface of the first laminated pattern;
• and
• a third semiconductor layer covering the first upper surface of the first laminated pattern, wherein the second semiconductor element includes:
• a second laminated pattern formed on the second semiconductor substrate, the second laminated pattern including a third end surface, a fourth end surface opposite the third end surface, a third side surface located between the third end surface and the fourth end surface, a fourth side surface located between the third end surface and the fourth end surface and opposite to the third side surface, and a third upper surface;
• a fourth semiconductor layer covering the third side surface of the second laminated pattern;
• a fifth semiconductor layer covering the fourth side surface of the second laminated pattern;
• and
• a sixth semiconductor layer covering the first upper surface of the second laminated pattern,
• wherein the first laminated pattern includes:
• a seventh semiconductor layer of a first conductive type formed on the first semiconductor substrate;
• an eighth semiconductor layer of a second conductive type formed on the seventh semiconductor layer, the second conductive type being opposite to the first conductive type;
• and
• a first emission layer formed at a boundary surface between the seventh semiconductor layer and the eighth semiconductor layer,
• wherein the second laminated pattern includes:
• a ninth semiconductor layer of the first conductive type formed on the second semiconductor substrate;
• a tenth semiconductor layer of the second conductive type formed on the ninth semiconductor layer;
• and
• a second emission layer formed at a boundary surface between the ninth semiconductor layer and the tenth semiconductor layer,
• wherein an index of refraction of each of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is smaller than an index of refraction of each of the seventh semiconductor layer and the eighth semiconductor layer,
• wherein an index of refraction of each of the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer is smaller than an index of refraction of each of the ninth semiconductor layer and the tenth semiconductor layer, and
• wherein the first semiconductor element and the second semiconductor element are connected to each other in series between the first wiring and the second wiring.

An electronic device comprising:

• a stem;
• a dielectric substrate formed on the stem, the dielectric substrate having a first wiring and a second wiring arranged along the first wiring;
• a first semiconductor chip mounted on the dielectric substrate, the first semiconductor chip having a semiconductor substrate, a first semiconductor element formed on the semiconductor substrate, and a second semiconductor element formed on the semiconductor substrate, an anode of the first semiconductor element being electrically connected to the first wiring, and a cathode of the second semiconductor element being electrically connected to the second wiring;
• a mounting substrate coupled to the dielectric substrate via a flexible substrate;
• and
• a second semiconductor chip mounted on the mounting substrate,
• wherein each of the first semiconductor element and the second semiconductor element includes:
• a laminated pattern formed on the semiconductor substrate, the laminated pattern including a first end surface, a second end surface opposite the first end surface, a first side surface located between the first end surface and the second end surface, a second side surface located between the first end surface and the second end surface and opposite to the first side surface, and an upper surface;
• a first semiconductor layer covering the first side surface of the laminated pattern;
• a second semiconductor layer covering the second side surface of the laminated pattern;
• and
• a third semiconductor layer covering the upper surface of the laminated pattern,
• wherein the laminated pattern of each of the first semiconductor element and the second semiconductor element includes:
• a fourth semiconductor layer of a first conductive type formed on the semiconductor substrate;
• a fifth semiconductor layer of a second conductive type formed on the fourth semiconductor layer, the second conductive type being opposite to the first conductive type;
• and
• an emission layer formed at a boundary surface between the fourth semiconductor layer and the fifth semiconductor layer,
• wherein an index of refraction of each of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is smaller than an index of refraction of each of the fourth semiconductor layer and the fifth semiconductor layer,
• wherein the first semiconductor element and the second semiconductor element are connected to each other in series between the first wiring and the second wiring, and
• wherein a driving circuit configured to drive the first semiconductor element and the second semiconductor element is provided in the second semiconductor chip.