Semiconductor chip including through electrodes, and semiconductor package including the same

A semiconductor chip comprising:

• a body portion with a front surface and a rear surface, the body portion being oriented in such a way that the rear surface is above the front surface;
• first and second through electrodes penetrating the body portion;
• a power pattern formed over the rear surface of the body portion and spaced apart from the first and second through electrodes;
• first and second connection patterns formed over the rear surface of the body portion and respectively connected to the first and second through electrodes;
• an interlayer insulating layer filling spaces between the power pattern and the first and second connection patterns;
• and
• first and second rear connection electrodes formed over the interlayer insulating layer and respectively connected to the first and second connection patterns,
• wherein the first rear connection electrode is simultaneously connected to the first connection pattern and a part of the power pattern that is adjacent to the first connection pattern, and
• wherein the second connection pattern is spaced apart from the power pattern.

A semiconductor package comprising:

• a first semiconductor chip including a body portion with a front surface and a rear surface, the body portion being oriented in such a way that the rear surface is above the front surface, first and second through electrodes penetrating the body portion, a power pattern formed over the rear surface of the body portion and spaced apart from the first and second through electrodes;
• first and second connection patterns formed over the rear surface of the body portion and respectively connected to the first and second through electrodes, an interlayer insulating layer filling spaces between the power pattern and the first and second connection patterns, first and second rear connection electrodes formed over the interlayer insulating layer and respectively connected to the first and second connection patterns, and a rear insulating layer formed over the interlayer insulating layer and the power pattern, filling a space between the first and second rear connection electrodes, where the first rear connection electrode is simultaneously connected to the first through electrode and a part of the power pattern that is adjacent to the first through electrode;
• and
• a second semiconductor chip including front connection electrodes directly bonded to the first and second rear connection electrodes, respectively, and a front insulating layer directly bonded to the rear insulating layer while filling spaces between the front connection electrodes.