Integrated circuit semiconductor device

An integrated circuit semiconductor device comprising:

• a first substrate having a first surface and a second surface opposite the first surface;
• a first through via passing from the first surface to the second surface of the first substrate;
• a heat transfer through via arranged apart from the first through via and passing from the first surface to the second surface of the first substrate;
• a cell-level portion arranged on the first surface of the first substrate and comprising a buried conductor connected to the first through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect;
• a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other;
• a heat transfer line connected to the heat transfer through via and the upper multi-layer interconnect layers, the heat transfer line formed in the cell-level portion and the signal wiring-level portion;
• a second substrate arranged on the signal wiring-level portion;
• a bonding-level portion arranged between the signal wiring-level portion and the second substrate and bonding the signal wiring-level portion to the second substrate, and comprising a bonding pad connected to an upper via of the upper vias;
• a power delivery network-level portion arranged under the second surface of the first substrate and comprising a plurality of lower multi-layer interconnect layers connected to the first through via and lower vias connecting the lower multi-layer interconnect layers to each other;
• and
• an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

An integrated circuit semiconductor device comprising:

• a substrate having a first surface and a second surface opposite the first surface;
• a rail through via passing between the first surface and the second surface of the substrate;
• a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect;
• a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other;
• a dummy substrate arranged on the signal wiring-level portion;
• a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to an upper via of the upper vias;
• a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other;
• and
• an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.