Middle-of-line interconnect structure and manufacturing method

A method of manufacturing an integrated circuit device, comprising:

• forming a lower inter-layer dielectric (ILD) layer over a substrate;
• forming an etch stop layer over the lower ILD layer;
• forming a lower conductive plug through the lower ILD layer and the etch stop layer over a source/drain region of a transistor structure;
• forming an upper ILD layer over the lower ILD layer and the etch stop layer;
• and
• forming an upper conductive plug through the upper ILD layer and extending into the etch stop layer;
• wherein the upper conductive plug is formed by forming a metal core followed by an annealing process to form an intermixing barrier layer lining an interface of the metal core and the upper ILD layer, a bottommost surface of the intermixing barrier layer overlying the etch stop layer.

A method of manufacturing an integrated circuit device, comprising:

• forming a lower inter-layer dielectric (ILD) layer over a substrate;
• forming an etch stop layer over the lower ILD layer;
• forming a lower barrier layer, the lower barrier layer surrounding inner sidewalls of the lower ILD layer and extending to a top surface of the etch stop layer;
• forming a lower conductive plug through the lower ILD layer and the etch stop layer reaching a source/drain region of a transistor structure, the lower conductive plug having a top surface below a top surface of the lower barrier layer;
• forming a capping layer on the lower conductive plug;
• and
• forming an upper conductive plug over the capping layer, the upper conductive plug extending beneath the capping layer and contacting a top surface and a bottom surface of the etch stop layer.