Metal-insulator-metal (MIM) capacitor structure for layer count reduction and lower capacitance variation

An integrated circuit (IC), comprising:

• a substrate;
• a first metal-insulator-metal (MIM) capacitor comprising:
• a first plate comprising a first metallization layer on a surface of the substrate,
• a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate, and
• a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer;
• an inductor comprising a portion of the second plate on the second portion of the surface of the substrate;
• and
• a second MIM capacitor, which comprises:
• the first plate on the surface of the substrate,
• a second MIM insulator layer on a second portion of the surface of the first plate;
• and
• a third plate on the second MIM insulator layer.