Semiconductor package and manufacturing method thereof

A semiconductor package comprising:

• a substrate comprising:
• a first substrate side;
• a second substrate side opposite the first substrate side;
• a recess portion in the first substrate side and extending toward the second substrate side;
• a plurality of recess conductive patterns in the recess portion;
• a dielectric layer having a first dielectric surface, a second dielectric surface, and side dielectric surfaces extending between the first dielectric surface and the second dielectric surface, wherein the recess portion extends from the first dielectric surface to the second dielectric surface between the side dielectric surfaces;
• a first conductive pattern at the first dielectric surface;
• a second conductive pattern at the second dielectric surface;
• and
• a conductive via that passes through the dielectric layer and electrically connects the first conductive pattern and the second conductive pattern;
• a passive element positioned in the recess portion of the substrate and comprising a first electrode and a second electrode, each electrically connected to a respective pattern of the plurality of recess conductive patterns;
• a semiconductor die mounted on the first dielectric surface and connected to the first conductive pattern;
• a layer of a single continuous encapsulating material that covers at least a first side and lateral sides of the passive element, and covers at least lateral sides of the semiconductor die and a first side of the semiconductor die facing away from the dielectric layer.

A method of manufacturing a semiconductor package, the method comprising:

• providing a substrate comprising:
• a first substrate surface;
• a second substrate surface opposite the first substrate surface;
• a recess portion in the first substrate surface and extending toward the second substrate surface;
• a plurality of recess conductive patterns in the recess portion;
• a dielectric layer having a first dielectric surface and a second dielectric surface, wherein the recess portion extends from the first dielectric surface to the second dielectric surface;
• a first conductive pattern at the first dielectric surface;
• a second conductive pattern at the second dielectric surface;
• and
• a conductive via that passes through the dielectric layer and electrically connects the first conductive pattern and the second conductive pattern;
• positioning a passive element in the recess portion of the substrate and electrically connecting a first electrode and a second electrode of the passive element to a respective pattern of the plurality of recess conductive patterns;
• mounting a semiconductor die on the first dielectric surface and connecting the semiconductor die to the first conductive pattern;
• and
• providing a layer of a single continuous encapsulating material that covers at least a first side and lateral sides of the passive element, and covers at least lateral sides of the semiconductor die and a first side of the semiconductor die facing away from the dielectric layer.