Integral redistribution layer for WCSP

A method, comprising:

• providing a wafer chip scale package (WCSP) including circuitry electrically coupled to die bond pads exposed by a passivation layer, further comprising a first dielectric layer the passivation layer;
• forming in the dielectric layer a first cavity comprising a center through-cavity bounded by a second cavity comprising a partial through-cavity;
• forming a pattern seed layer that lines the first and second cavities;
• forming a second dielectric layer on the first dielectric layer that covers the first and second cavities;
• forming an aperture in the second dielectric layer over the second cavity;
• plating a metal in the first and second cavities and the aperture;
• and
• positioning a solder ball on the metal in the aperture.

A wafer chip scale package (WCSP), comprising:

• a substrate comprising a semiconductor surface including circuitry electrically connected to die bond pads exposed by a passivation layer, further comprising a dielectric layer covering the passivation layer;
• a first cavity through the dielectric layer bounded by a second cavity partially through the dielectric layer;
• a second dielectric layer covering the dielectric layer except for an aperture over the second cavity;
• a metal filling the first and second cavities and the aperture and contacting at least one of the die bond pads;
• and
• a solder ball on the metal within the aperture.