Virtual metrology for feature profile prediction in the production of memory devices

A method, comprising:

• fabricating a plurality of an integrated circuit using a first set of processing parameters, the integrated circuit comprising a plurality of circuitry layers formed on a substrate;
• selecting a first plurality of the integrated circuit as first test samples;
• performing one or more first tests on the first test samples to determine a corresponding one or more metrology data values for each of the first test samples;
• performing one or more second tests on the first plurality of the integrated circuit, the one or more second tests including determining values for electrical properties of a first subset of the circuitry layers;
• performing a machine learning process to determine a correlation between the metrology data values and results of the one or more second tests;
• selecting a second plurality of the integrated circuit;
• determining, for the second plurality of the integrated circuit, values for the electrical properties of a first plurality of the circuitry layers, the first plurality of the circuitry layers including circuitry layers other than the first subset of the circuitry layers;
• interpolating metrology data values for the first plurality of the circuitry layers of the second plurality of the integrated circuit from the correlation and results of the values for the electrical properties of the first plurality of the circuitry layers;
• based the interpolated metrology data values, adjusting the processing parameters;
• and
• fabricating the integrated circuit using the adjusted processing parameters.

A system, comprising:

• one or more processors, the one or more processors configured to:
• receive results of one or more first tests on a plurality of first test samples from a first plurality of an integrated circuit, the integrated circuit comprising a plurality of circuitry layers formed on a substrate;
• determine from the one or more first tests a corresponding one or more metrology data values for each of the first test samples;
• receive results of one or more second tests on the first test samples of the integrated circuit, the one or more second tests including determining values for electrical properties of a first subset of the circuitry layers;
• perform a machine learning process to determine a correlation between the metrology data values and results of the one or more second tests;
• receive, for a second plurality of the integrated circuit, values for the electrical properties of a first plurality of the circuitry layers, the first plurality of the circuitry layers including circuitry layers other than the first subset of the circuitry layers;
• and
• interpolate metrology data values for the first plurality of the circuitry layers of the second plurality of the integrated circuit from the correlation and results of the values for the electrical properties of the first plurality of the circuitry layers.