Nanosheet device with different gate lengths in same stack

A method for forming a semiconductor device comprising:

• providing a nanosheet stack on a substrate comprising a bottom superlattice structure and a top superlattice structure separated from one another by a barrier insulator layer, where each of the bottom and top superlattice structures comprises alternating silicon and silicon germanium nanosheet layers;
• selectively etching the nanosheet stack to form a nanosheet transistor stack on the substrate;
• processing the nanosheet transistor stack to form first remnant silicon germanium nanosheet layers in at least the bottom superlattice structure having a first gate length dimension;
• and then subsequently
• processing the nanosheet transistor stack to form second remnant silicon germanium nanosheet layers in the top superlattice structure having a second gate length dimension that is shorter than the first gate length dimension;
• forming planarized epitaxial semiconductor regions adjacent to the bottom superlattice structure and a top superlattice structure;
• partially etching the planarized epitaxial semiconductor regions to form first epitaxial source/drain semiconductor regions adjacent to the bottom superlattice structure which expose the top superlattice structure;
• forming a directional insulator layer to cover the first epitaxial source/drain semiconductor regions;
• forming second epitaxial semiconductor regions adjacent to the top superlattice structure,
• where the first and second epitaxial source/drain semiconductor regions are electrically isolated from one another by an insulating directional insulator layer;
• and
• selectively processing the nanosheet transistor stack to simultaneously form (a) bottom gate electrodes which replace the first remnant silicon germanium nanosheet layers in the bottom superlattice structure, thereby forming a bottom nanosheet transistor comprising the bottom gate electrodes having the first gate length dimension, the silicon nanosheet layers from the bottom superlattice structure, and the first epitaxial source/drain semiconductor regions, and (b) top gate electrodes which replace the second remnant silicon germanium nanosheet layers in the top superlattice structure, thereby forming a top nanosheet transistor comprising the top gate electrodes having the second gate length dimension that is shorter than the first gate length dimension, the silicon nanosheet layers from the top superlattice structure, and the second epitaxial source/drain semiconductor regions.