Structure for fringing capacitance control

A method, comprising:

• forming a plurality of fin field effect transistors (finFETs) that share a gate structure;
• removing portions of the gate structure between adjacent fin structures of the plurality of finFETs to form openings, wherein removing portions of the gate structure comprises forming a recess in a dielectric layer between the adjacent fin structures with a vertical depth between about 50 nm and about 100 nm below a top surface of the dielectric layer;
• and
• inserting, into the openings, an insulating material of substantially constant width that electrically isolates the finFETs from one another, wherein inserting the insulating material comprises forming an air gap in the insulating material occupying the opening.

A method of producing transistors, the method comprising:

• forming a plurality of fin structures on a semiconductor substrate;
• forming a metal gate structure that wraps around each of the plurality of fin structures;
• and
• replacing portions of the metal gate structure with a low-k dielectric material to electrically isolate the plurality of fin structures from one another, wherein replacing portions of the metal gate structure comprises:
• cutting the metal gate structure between, and substantially parallel to, adjacent fin structures in the plurality of fin structures to form cuts with a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the semiconductor substrate, wherein the cutting comprises forming a recess in a dielectric layer between fin structures in the plurality of fin structures;
• depositing, into the cuts, a multi-layer dielectric stack of substantially constant width, comprising a silicon nitride liner and silicon oxide;
• and
• forming an air gap in the multi-layer dielectric stack within the cuts.