Methods of reducing parasitic capacitance in semiconductor devices

A semiconductor structure, comprising:

• a semiconductor fin disposed over a substrate;
• a metal gate stack (MG) disposed over the semiconductor fin;
• a source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the MG;
• an S/D contact disposed over the S/D feature;
• an air gap disposed between the S/D contact and the MG, wherein a first portion of the air gap is disposed along a sidewall of the S/D contact, wherein a second portion of the air gap is disposed along a sidewall of the S/D feature, and wherein a third portion of the air gap is disposed at an interface between the S/D contact and the S/D feature;
• and
• a dielectric layer partially filling the first portion of the air gap.

A semiconductor structure, comprising:

• a source/drain (S/D) feature disposed over a semiconductor fin;
• a metal gate stack disposed adjacent to the S/D feature and separated from the S/D feature by a first air gap;
• an S/D contact disposed over the S/D feature and separated from the metal gate stack by the first air gap;
• a silicide layer disposed between the S/D feature and the S/D contact, wherein a portion of a bottom surface of the silicide layer is separated from the S/D feature along a vertical direction by a second air gap;
• and
• a seal layer disposed over the first air gap.